FloorPlan

Hi Everyone,

In this post i will be covering the Basics of Floorplanning and how is it done.

Let me start with the question, what is floorplanning? In simple words, Floorplanning is nothing but trying to find good places for the blocks on the floor or chip whatever, so that it minimizes the wirelength and so the delay. It is something like construction plan for a house. When you draw a plan for house you try to place the kitchen, bedroom, rest room, hall and dinning hall according to the area constraints and the rooms which should be close. Similarly in Floorplan, we will try to place the blocks which should be near and others far.

At floorplan level we have two kinds of Macro, called the Hard Macro and the Soft macro. The one which cannot be moved at any point of the ASIC flow are called Hard Macros. These macros come in a fixed position when we get a floorplan file. The one that can have its aspect ratio and connector locations, variable is called Soft Macro. We have standard cells which are generally placed in rows have theirs widths, variable, in the sense these are flexible cells.

Now that we have understood some of the basic terminology, let us try to place these cells or blocks. Let us say i have given a design to a tool and it has brought out the seed (initial floorplan is called seed). There are so many approaches to solve problem of long wire lengths. Basic and most common practice is based on number of interconnects between the cells or blocks. Needless to say, that we have to place the blocks or cells which are highly connected, nearer too each. By doing so we reduce the wirelength required to connect those blocks.

Some times we see a better timing, when we replace a particular cell or block with the existing one. And at times, we see that one particular placement of a soft macro improves the timing rather than keeping it at the place where the tool has suggested us. Once we are done with this we have the final floorplan ready. From here we will proceed with the Power plan.
The resource for all the above definition is from the World's best search engine also called Google. Please search words which you didn't understand in http://www.google.com and know more about them.

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Power Plan

Hi Everyone,

In the previous post, i have discussed on Floorplan. In the current session, i will try to explain the importance of Power plan and why it is needed.

Each and every circuitry in the IC needs power. So, the Power planning must be done in order to achieve the ultimate goal of Power dissipation reduction. Now, here you may get the doubt, like How can we reduce the power dissipation by mere Power Planning? The answer is, in an IC we have few power hungry circuits like clock which eat up most of the power, which has to be placed propeerly so as to reduce the amount of power dissipated in transmitting the power to it and the other way of Power dissipation is through IR drops.

We need to design a proper mesh so as to deliver Power to each and every circuit with minimal loss. As we know a long wire will have resistance which is proportional to its length. This can be understood with mere formula for resistance as shown below
                                                      R=k*L/W
where k=the resistivity constant(sorry could find rho letter here)
L=length of the wire
W=width of the wire

So from the equation we can say that if we have long wire, it means it has high resistance, if we dont increase the width. The point is, Power has to be transmitted through such wires to reach the corner most point of the IC. It means, if we don't select the proper mesh structure, it is sure that we end up losing lots of power as heat and hence spoil the IC. So we need to design a effective Power Mesh and hence need to do Power Planning.

There are other factors like Electro Migrations(discussed in my very first blog), which should be taken care of while doing the Power Planning.

There are three techniques in designing a Power mesh. they are.
1)2-D layer Design
2)1-D layer design
3)Row based design

 In 2-D layer design we use one layer for Vdd and one for ground. In 1-D layer design we use only one layer for both, in the sense the system or block is partitioned and routed accordingly. Row based design is generally used for standard cells which are placed in row fashion.
The resource for all the above explanation is from the World's best search engine also called Google. Please search difficult words in http://www.google.com and know more about them.

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RTL to Netlist

Hi Everyone,

Today, I'm gonna throw some light on how the RTL code is synthesized to Netlist.

The synthesis of a netlist from the RTL code is done by a compiler. The following diagram shows the same.

 The above diagram shows that the compilers takes the inputs like SDC, Library and .lib, and give the Netlist as the output. The first question that pops into our mind is What is SDC and .lib?
     Let us see what is SDC. It is the representation of design intent, including the timing, power and area constraints, In simple language it contains the information related to timing, power and area, and conditions applied on them. (ref: http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html)
     Let us see what is .lib. It is the ASCII representation of timing and power. To explain this let me tell you a simple experiment. Let us suppose that we have an AND gate with A, B as inputs and C as the output. So, now we know that the output C will be equal to one of the input if the other input is '1'. This is like a common sense for us, but for software it is not. so there comes this .lib file, it will tell how to send the input to the output for given conditions. (ref: http://www.csee.umbc.edu/~cpatel2/links/641/slides/lect05_LIB.pdf)

Now that we have understood what are these SDC and .lib files. Lets see the flow how the Netlist generation is done.
The steps followed while generating the netlist are as follows:
(i) High level RTL optimization
(ii) RTL to unoptimized boolean logic
(iii) Optimization
(iv) Mapping to available standard cells

During High level RTL optimization, the number of high level blocks like Adders, Multipliers etc will be reduced by placing conditional logics. For example, if we have two adders which are adding two numbers based on the selection of input, in such cases we replace the unwanted adder with mux and its select input will decide which to take.

After the RTL optimization, the optimized code is mapped to the unoptimized boolean logic gates. In this step the boolean operations are replaced by unoptimized boolean logic.

In this step, we might not see a design with proper performance, as we may have redundant gates placed. In optimization step, this kind of things will be taken care of.

In the final step, the unoptimized logic can be optimized and performance can be enhanced by replacing some of the cell with standard cells. Once this is done, we get our final Netlist.

The resource for all the above definition is from the World's best search engine also called Google. Please search this words in http://www.google.com and know more about them.

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Pre-requisites for Backend Design

Hi Everyone,

Today let us start with some basic pre-requisites for Backend Design.

What is Setup time?
It is the time for which the data should be valid before the clock edge, so as to capture the data without any violations.

What is Hold time?
It is the time for which the data should be valid after the clock edge, so as to latch the data without any violations.

What is Fanout?
It is the ability of a logic gate to drive a no. of i/p's of other logic gates.

What is Slew?
The rate of change of Output with respect to time. Some times also called as Output Transition.

What is Latency?
It is the delay between the signal source and the signal network delay.

What is Skew?
It is the difference between the arrival times of a signal from its origin point to different destination points.
       What is Global Skew?
        It is the difference between the arrival times of the signal at Inter chip level.
       What is Local Skew?
       It is the difference between the arrival times of the signal at Intra chip level.

What is Launch Clock?
It is the clock wherein the data is launched and will be captured at the next possible flop.
What is Capture Clock?
It is the clock wherein the data is captured, which is coming from the launch flop.

What is On-Chip Variation?
It is minor difference on different parts of the chip within one operating conditions. On-Chip Variation delays vary across a single die due to
            (i) Variation in the manufacturing process (P)
            (ii) Variation in Voltage (due to IR drops)
            (iii) Variation in the temperature (due to local hot spots etc)

What is Common Path Pessimism?
The pessimism caused due to the derating factors applied on the common part of a signal is called Common Path Pessimism.

What is Crosstalk delay?
It is defined as the impact of aggressor net over the victim net causing an additional or subtrational delay in victim net's signal propagation time.
What is Crosstalk noise?
It is defined as the glitch caused in the victim net's signal due to the switching in aggressor net.
What is Crosstalk?
It is the impact of aggressor net over the victim net.

What is Electromigration?
It is the transport of material due to the movement of ions, caused by the momentum transfer between the electrons and the atoms in the metal.

What is Congestion?
Congestion means to overflow or overfill.

What is Placement Congestion?
Congestion caused due to excess accumulation of blocks or cells at one point.

What is Routing Congestion?
A design is said to exhibit Routing Congestion when the demand for the routing resources in some region within the design exceed their supply.

The resource for all the above definition is from the World's best search engine also called Google. Please search this words in http://www.google.com and know more about them.

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