Hi Everyone,
Today, I'm gonna throw some light on how the RTL code is synthesized to Netlist.
The synthesis of a netlist from the RTL code is done by a compiler. The following diagram shows the same.
The
above diagram shows that the compilers takes the inputs like SDC,
Library and .lib, and give the Netlist as the output. The first question
that pops into our mind is What is SDC and .lib?
Let us see what is SDC. It is the representation of design intent, including the timing, power and area constraints, In simple language it contains the information related to timing, power and area, and conditions applied on them. (ref: http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html)
Let us see what is .lib. It is the ASCII representation of timing and power. To explain this let me tell you a simple experiment. Let us suppose that we have an AND gate with A, B as inputs and C as the output. So, now we know that the output C will be equal to one of the input if the other input is '1'. This is like a common sense for us, but for software it is not. so there comes this .lib file, it will tell how to send the input to the output for given conditions. (ref: http://www.csee.umbc.edu/~cpatel2/links/641/slides/lect05_LIB.pdf)
Now that we have understood what are these SDC and .lib files. Lets see the flow how the Netlist generation is done.
The steps followed while generating the netlist are as follows:
(i) High level RTL optimization
(ii) RTL to unoptimized boolean logic
(iii) Optimization
(iv) Mapping to available standard cells
During High level RTL optimization, the number of high level blocks like Adders, Multipliers etc will be reduced by placing conditional logics. For example, if we have two adders which are adding two numbers based on the selection of input, in such cases we replace the unwanted adder with mux and its select input will decide which to take.
After the RTL optimization, the optimized code is mapped to the unoptimized boolean logic gates. In this step the boolean operations are replaced by unoptimized boolean logic.
In this step, we might not see a design with proper performance, as we may have redundant gates placed. In optimization step, this kind of things will be taken care of.
In the final step, the unoptimized logic can be optimized and performance can be enhanced by replacing some of the cell with standard cells. Once this is done, we get our final Netlist.
The resource for all the above definition is from the World's best search engine also called Google. Please search this words in http://www.google.com and know more about them.
Thank You
Today, I'm gonna throw some light on how the RTL code is synthesized to Netlist.
The synthesis of a netlist from the RTL code is done by a compiler. The following diagram shows the same.
Let us see what is SDC. It is the representation of design intent, including the timing, power and area constraints, In simple language it contains the information related to timing, power and area, and conditions applied on them. (ref: http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html)
Let us see what is .lib. It is the ASCII representation of timing and power. To explain this let me tell you a simple experiment. Let us suppose that we have an AND gate with A, B as inputs and C as the output. So, now we know that the output C will be equal to one of the input if the other input is '1'. This is like a common sense for us, but for software it is not. so there comes this .lib file, it will tell how to send the input to the output for given conditions. (ref: http://www.csee.umbc.edu/~cpatel2/links/641/slides/lect05_LIB.pdf)
Now that we have understood what are these SDC and .lib files. Lets see the flow how the Netlist generation is done.
The steps followed while generating the netlist are as follows:
(i) High level RTL optimization
(ii) RTL to unoptimized boolean logic
(iii) Optimization
(iv) Mapping to available standard cells
During High level RTL optimization, the number of high level blocks like Adders, Multipliers etc will be reduced by placing conditional logics. For example, if we have two adders which are adding two numbers based on the selection of input, in such cases we replace the unwanted adder with mux and its select input will decide which to take.
After the RTL optimization, the optimized code is mapped to the unoptimized boolean logic gates. In this step the boolean operations are replaced by unoptimized boolean logic.
In this step, we might not see a design with proper performance, as we may have redundant gates placed. In optimization step, this kind of things will be taken care of.
In the final step, the unoptimized logic can be optimized and performance can be enhanced by replacing some of the cell with standard cells. Once this is done, we get our final Netlist.
The resource for all the above definition is from the World's best search engine also called Google. Please search this words in http://www.google.com and know more about them.
Thank You
Thanks a lot
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